The present invention relates to a semiconductor memory device; and, more particularly, to a synchronous semiconductor memory device having a pipe register, which stores and outputs data at a high speed by using a pipeline scheme.
In a read operation, a synchronous memory device temporarily stores data to a temporary storage unit and then outputs the data through a data output pin in synchronization with an external clock. That temporary storage unit is called a pipe register.
FIGS. 1 and 1A-1D are schematic diagrams showing a synchronous memory device having a conventional pipe register.
Referring to FIGS. 1 and 1A-1D the synchronous memory device includes a plurality of pipe registers, each of which is coupled to four pairs of global I/O lines and complementary global I/O lines. By combining signals of the four pairs, a common prefetch signal PFETCH[0:2] is generated. The pipe registers, coupled to eight global I/O lines and complementary global I/O lines are commonly controlled by the common prefetch signal PFETCH[0:2].
As shown in FIG. 1A, a prefetch signal generator 100 is coupled to four pairs of global I/O lines and complementary global I/O lines GIO less than 4 greater than , GIOZ less than 4 greater than , GIO less than 5 greater than , GIOZ less than 5 greater than , GIO less than 6 greater than , GIOZ less than 6 greater than , GIO less than 7 greater than , GIOZ less than 7 greater than .
A prefetch signal generator 110 is coupled to four pairs of global I/O lines and complementary global I/O lines GIO less than 12 greater than , GIOZ less than 12 greater than , GIO less than 13 greater than , GIOZ less than 13 greater than , GIO less than 14 greater than , GIOZ less than 14 greater than , GIO less than 15 greater than , GIOZ less than 15 greater than . Pipe registers 120 to 127 are respectively coupled to the global I/O lines and the complementary global I/O lines GIO less than 0 greater than and GIOZ less than 0 greater than , GIO less than 1 greater than and GIOZ less than 1 greater than , GIO less than 2 greater than and GIOZ less than 2 greater than , GIO less than 3 greater than and GIOZ less than 3 greater than , GIO less than 4 greater than and GIOZ less than 4 greater than , GIO less than 5 greater than and GIOZ less than 5 greater than , GIO less than 6 greater than and GIOZ less than 6 greater than , GIO less than 7 greater than and GIOZ less than 7] greater than , and receives the common prefetch signal PFETCH[0:2] from the prefetch signal generator 100.
Pipe registers 128 to 135 are respectively coupled to four pairs of global I/O lines and complementary global I/O lines GIO less than 8 greater than and GIOZ less than 8 greater than , GIO less than 9 greater than , GIOZ less than 9 greater than , GIO less than 10 greater than , GIOZ less than 10 greater than , GIO less than 11 greater than , GIOZ less than 11 greater than , GIO less than 12 greater than , GIOZ less than 12 greater than , GIO less than 13 greater than , GIOZ less than 13 greater than , GIO less than 14 greater than , GIOZ less than 14 greater than , GIO less than 15 greater than , GIOZ less than 15 greater than , and receives the common prefetch signal PFETCH[0:2] from the prefetch signal generator 110.
Data output buffers 136 to 151 are coupled to output terminals of the pipe register 120 to 135, respectively.
A pipe counter 160 generates a pipe counter signal POCNT to the pipe registers 128 to 135. At this time, the data output is controlled by the pipe counter signal POCNT.
In such a synchronous memory device, the data on each of the global I/O lines and the complementary global I/O lines have different skews due to loads thereof. Therefore, a pulse width of the common prefetch signal PFETCH[0:2] should be widened as much as the skew between the global I/O line and the complementary global I/O line.
As a result, it is difficult for the conventional synchronous memory device to latch the data into the pipe registers in a high speed in case where the prefetch signal PFETCH[0:2] has a wide pulse width.
FIG. 2 is a circuit diagram showing a conventional pipe register. The conventional pipe register includes three storage units 200, 210 and 220.
As shown in FIG. 2, since the conventional pipe register clears data stored in storage unit 200 in response to a clear signal CL1, a cycle time is increased so that it is difficult to obtain a high speed of operation in the synchronous memory device.
It is, therefore, an object of the present invention to provide a synchronous memory device having a pipe register, which stores and outputs data at a high speed by using a pipeline scheme.
In accordance with an aspect of the present invention, there is provided a pipe register for use in a semiconductor memory device, wherein said semiconductor memory device includes global input/output (I/O) lines, complementary global I/O lines, and pipe registers, coupled to said global I/O lines and said complementary global I/O lines, for detecting the data loaded on said global I/O lines and complementary global I/O lines to store the data, said pipe register comprising: a data detecting means, coupled to said global I/O lines and complementary global I/O lines, for detecting whether the data is loaded on said global I/O lines and complementary global I/O lines; a control signal generating means for sensing edges of the data loaded on the global I/O line and the complementary global I/O line to generate a rising edge sensing signal and a falling edge sensing signal; and a plurality of storage means for storing the data loaded on said global I/O lines and said complementary global I/O lines in response to a reset signal, the falling edge sensing signal and the rising edge sensing signal and for outputting the data in response to the pipe counter signal outputted from said pipe counting means.
Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:
FIGS. 1 and 1A-1D are schematic diagrams illustrating a synchronous memory device having a conventional pipe register;
FIG. 2 is a circuit diagram illustrating a conventional pipe register;
FIGS. 3 and 3A-3D are block diagrams illustrating a synchronous memory device having a pipe register in accordance with an embodiment of the present invention;
FIGS. 4 and 4A-4D are circuit diagrams illustrating a pipe register shown in FIG. 3; and
FIGS. 5A and 5B are timing charts of signals in a pipe-register shown in FIG. 4.